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CDB8952
Crystal LAN? 10Base-T and 100Base-X Transceiver
NOTE: Physical address 00000 is a special broadcast
address. All devices will respond to this address
in addition to the one selected using S3. Setting
S3 to 00000 will cause the CS8952 to set the
ISOLATE bit in the Basic Mode Control Regis-
ter, isolating itself from all MII signals except
MDC and MDIO. It will remain isolated until this
bit is cleared.
cle is required before any changes in these jumper
settings will take effect.
HDR6, HDR7 - Transmit Slew Rate Select 0 and 1.
These headers are used to select the rise and fall
times of the 100BASE-TX transmitter output
waveform as indicated in Table 5.
Care should be taken when reading from phys-
ical address 00000 when multiple devices
reside on the same MII.
HDR1 - MII Drive Select. When this header is left
open, the CS8952 MII drivers will conform to the
IEEE 802.3u specification. When a shorting cap is
installed, the CS8952 MII drivers will be reduced
to 4mA.
HDR7
(TXSLEW1)
pins 2-3 shorted
open
pins 1-2 shorted
pins 2-3 shorted
open
pins 1-2 shorted
pins 2-3 shorted
HDR6
(TXSLEW0)
pins 2-3 shorted
pins 2-3 shorted
pins 2-3 shorted
open
open
open
pins 1-2 shorted
Rise/Fall
Time
0.5 ns
1.0 ns
1.5 ns
2.0 ns
2.5 ns
3.0 ns
3.5 ns
The CS8952 checks the status of HDR1 only dur-
ing power-on or reset. A reset or power cycle is re-
quired before any changes in this jumper setting
open pins 1-2 shorted
pins 1-2 shorted pins 1-2 shorted
Table 5. Transmit Slew Rate
4.0 ns
4.5 ns
will take effect.
HDR4, HDR5 - Auto-Negotiation Select 0 and 1.
These headers are used to select the forced or ad-
vertised auto-negotiation modes as indicated in Ta-
ble 4.
HDR15 - Table 6 describes the effect of shorting
the listed pin pairs.
HDR34 - Test 0. This header is for factory test pur-
poses only, and should be left open for normal op-
eration.
HDR5
(AN1)
pins 2-3
HDR4
(AN0)
open
Speed
10
Forced/ Full/Hal
Auto f Duplex
Forced Half
HDR35 - Test 1. This header is for factory test pur-
poses only, and should be left open for normal op-
shorted
eration.
pins 1-2
shorted
open
open
pins 2-3
10
100
Forced
Forced
Full
Half
HDR42 - TX_CLK Source Select. This header, in
conjunction with HDR43, is used to select the
shorted
TX_CLK source. When pins 1 and 2 are selected,
open
open
pins 2-3
pins 1-2
shorted
open
pins 2-3
100
100/10
10
Forced
Auto
Auto
Full
Full/Half
Half
TX_CLK is supplied from the CS8952 CLK25 out-
put. When pins 2 and 3 are shorted, TX_CLK is
supplied externally from J1. When no shorting cap
shorted
shorted
is installed, HDR43 must be configured so that
pins 2-3
shorted
pins 1-2
pins 1-2
shorted
pins 2-3
10
100
Auto
Auto
Full
Half
TX_CLK is an output from the CS8952.
NOTE: No shorting cap should be installed on this
shorted
shorted
header when TX_CLK is configured as an out-
pins 1-2
pins 1-2
100
Auto
Full
put (see HDR43).
shorted
shorted
HDR43 - TX_CLK Mode Select. (Table 7)
Table 4. Auto-Negotiation Select
The CS8952 checks the status of HDR4 and HDR5
only during power-on or reset. A reset or power cy-
The CS8952 checks the status of HDR43 only dur-
ing power-on or reset. A reset or power cycle is re-
quired before any changes in this jumper setting
will take effect.
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
DS206DB2
3
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